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Daly, A. Chandrakasan, and W. Dehaene Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications.


An important milestone in this transition has been the release of the IEEE In this paper, we evaluate the potential of an Starting from measurements carried out on the off-the-shelf radio, effective radio activation and link adaptation policies are derived. It is shown that, in a typical sensor network scenario, the average power per node can be reduced down to mW.

Next, the energy consumption breakdown between the different phases of a packet transmission is presented, indicating which part of the transceiver architecture can most effectively be optimized in order to further reduce the radio power, enabling self-powered wireless microsensor networks. Rai and R. These sensors are either randomly or deterministically placed within a certain region to monitor events that are spatially and temporally independent of each other. A cheap and effective approach is to replace the sensor nodes in due course instead of replenishing of their batteries.

Thus, the objective is to find the replacement time Tr such that none of the sensor nodes run out of their batteries disconnected before Tr. An alternative way of formulating this problem is to find the lifetime T of the network, which is defined as the time after which the first node in the network disconnects.

Studies evaluating the lifetime model of the sensor networks have been done before in [1], [2], [4]. However, the primary difference between previous approaches and our work is that we specifically model a data generation process at an individual sensor node, where each node covers certain area and the amount of data generated at a node is proportional to its coverage area.

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Segura, and A. Keshavarzi As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations.

In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. Hassan, M. Anis, A. El Daher, and M. The first algorithm is a connection-based packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the blocks activities is considered.

After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.

Srinivasan, L. Li, and N. Vijaykrishnan In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system.

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We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially. Mukhopadhyay, S. Bhunia, and K. Roy In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band- tunneling BTBT leakage, results in the large increase of total leakage power in a logic circuit.

Interconnect-Centric Design for Advanced SOC and NOC

Leakage components interact with each other in device level through device geometry, doping profile and also in the circuit level through node voltages. Due to the circuit level interaction of the different leakage components, the leakage of a logic gate strongly depends on the circuit topology i. In this paper, for the first time, we have analyzed loading effect on leakage and proposed a method to accurately estimate the total leakage in a logic circuit, from its logic level description considering the impact of loading and transistor stacking.

Tsai, V. Narayaynan, Y.

Other relevant bibliographies:

Xie, and M. Irwin On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve Nollet, T. Marescaux, P. Avasare, J. Mignolet, and D. Verkest Run-time management of both communication and computation resources in a heterogeneous Network-on-Chip NoC is a challenging task.

First, platform resources need to be assigned in a fast and efficient way. Secondly, the resources might need to be reallocated when platform conditions or user requirements change. We developed a run-time resource management scheme that is able to efficiently manage a NoC containing fine grain reconfigurable hardware tiles. This paper details our task assignment heuristic and two run-time task migration mechanisms that deal with the message consistency problem in a NoC.

We show that specific reconfigurable hardware tile support improves performance of the heuristic and that task migration mechanisms need to be tailored to on-chip networks. Hung, W. Bishop, and A. Kennings Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. This paper presents an implementation of a tightly-coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.

Genko, G. De Micheli, D. Atienza, J. Mendias, R.

Hermida, and F. Networks-On-Chip NoC provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort.

Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures. Nollet, P. Verkest Run-time task migration in a heterogeneous multiprocessor System-on-Chip MP-SoC is a challenge that requires cooperation between the task and the operating system.

In task migration, minimization of the overhead during normal task execution i. We introduce a novel technique that reuses the processor's debug registers in order to minimize the overhead during normal execution. This paper explains our task migration proof-of-concept setup and compares it to the state-of-the art.

By reusing existing hardware and software functionality our approach reduces the run time overhead.

CSDL | IEEE Computer Society

Stuijk, T. Basten, B. Mesman, and M. Geilen This extended abstract presents models to derive timing and resource usage numbers for an application when distant, shared memories are used in an important class of future embedded platforms, namely network-on-chip-based multiprocessors. Muller, Y.